1. Field of the Invention
The present invention relates to a semiconductor device including a plurality of circuits for performing predetermined processing to an inputted signal, and furthermore relates to a circuit technique for reducing amount of margin, which is secured when a circuit is designed in order to allow circuit operation even if performance of a manufactured integrated-circuit is varied, so that a semiconductor chip may operate with optimum performance of the circuit.
2. Description of the Related Art
With progress of size reduction in semiconductor manufacturing process, variation is increased in threshold voltage (Vth) of a MOS transistor. When Vth of a manufactured MOS transistor is decreased due to variation in Vth, since a drive current of the MOS transistor is increased, operable operation speed of a circuit is increased. Conversely, when Vth of a manufactured MOS transistor is increased due to variation in Vth, since a drive current of the MOS transistor is decreased, operable operation speed of a circuit is decreased. When processing size is decreased to less than 90 nm in the semiconductor manufacturing process, difference in speed caused by variation is increased due to increase in variation of Vth, leading to difficulty in determination of operation speed of a circuit. Particularly, in case of using a technique called FV control in which each of operation frequency and power voltage of a circuit is changed depending on required performance of the circuit, since operable frequency of the circuit is different depending on power voltage, when the circuit is designed, operation frequency is hardly determined to meet any power voltage depending on variation. Therefore, when optimum operation frequency can be determined by measuring a characteristic of a manufactured circuit, performance of the manufactured circuit can be adequately used. For example, JP-A-2003-273234 describes a technique where timing of a clock inputted into a circuit is controlled to measure performance of the circuit.